Introducing Daily Logs

A journal from myself to myself.

Hello, World!

Inaugurating my personal homepage.

Hi, I’m Abhishek.

Since early childhood I have spent a large chunk of my time building and working on tech - electronic circuits and software professionally and in my own time as personal learning projects as well. This is my personal homepage - home to my technical (which would have previously been under “The Embedded Kitchen” banner) as well as personal content, organized in separate sections.

Read my blog by clicking on this link. Opinions expressed within are my own.

If you’d like to stay in touch or be updated when I post new content here, please leave me a message at my email or follow me on Twitter. At some point I will add an email subscription widget here where you can enter your email address and receive updates.


  • Embedded Systems
  • Hardware Design (schematics/layout/manufacturing)
  • FPGAs
  • Augmented Reality
  • Brain-Computer Interfaces
  • Non-technical: Music (vocals and piano), Journalling and Reading


  • M.Tech. in Visual Information and Embedded Systems, 2016-17

    Indian Institute of Technology (IIT), Kharagpur, India

  • B.Tech. in Electronics and Electrical Communication Engineering (E&ECE), 2012-16

    Indian Institute of Technology (IIT), Kharagpur, India


Under construction. Check back for more!


Professional Experience


Product Applications Engineer

Analog Devices, Inc. (ADI)

Aug 2017 – Present Bangalore, India

Driving internal technical projects across different teams and also customer engagement through work including but not limited to:

  • Leading design of hardware systems from schematic to layout to contract manufacturing to bring-up and initial validation (~10 designs over 3 years);
  • Software development for both consumer and embedded devices;
  • Supporting ADI’s demonstrations at tech conferences;
  • Validating systems intended for customer use;
  • EMC testing of hardware to automotive standards (CISPR 25, ISO 11452-2).

Hardware Engineering Intern

Google LLC

May 2016 – Jul 2016 Mountain View, California, USA
Working with a leading edge ASIC design team to explore different configurational choices of logic cells that would lead to optimized total cost of ownership (TCO) of the entire chip - including not just the fabrication cost of the chip but also post-deployment total power consumption in the data center. Dealt with parsing information from large log reports from silicon synthesis tools and subsequent data processing, modeling, analysis and reporting.